1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a protective transistor for protecting an internal circuit against an electrostatic discharge (ESD)-induced destruction.
2. Description of the Related Art
A conventional protective circuit for protecting a semiconductor integrated circuit (IC) against an ESD-induced destruction is described, for example, in JP-A-92-122059. FIG. 1 is an equivalent circuit of an input/output section of the conventional protective circuit as mentioned above. FIG. 2 is a plan view of a pattern layout therefor and FIG. 3 is a cross-sectional view taken along line III--III in FIG. 2. The input/output section has a function for both inputting and outputting a signal between an internal circuit 50 and the input/output terminal 1 of the semiconductor device.
In the circuit shown in FIG. 1, when a high-voltage surge pulse is applied to the input/output metallic terminal 1 due to an electrostatic charge entering from outside the device, a surge current flows through parasitic capacitors of an output transistor 2 and a signal path 100 as well as through an input resistor 3 and a signal path 101 to an internal circuit 50, thereby causing a destruction of the semiconductor device. For avoiding such a destruction, a protective transistor 4 is provided in a vicinity of the input/output terminal 1 for protecting both of the output transistor 2 and the internal circuit 50 against the destruction through forming a discharge path. The protective transistor 4 is implemented by a bipolar transistor having a high current capacity. When a high-voltage surge pulse is applied to a collector of the protective transistor 4, the protective transistor 4 turns conductive to thereby clamp the applied voltage below an absolute breakdown voltage of the device.
As shown in FIG. 3, the output transistor 2 is implemented by an NMOSFET having a lightly doped drain (LDD) structure including an N-type diffused layers 6 and 7 formed in a P-type semiconductor substrate 5 together with a gate electrode 8. A gate oxide film 15 is formed between the semiconductor substrate 5 and the gate electrode 8. N-type diffused layer 6 constituting a source of the output transistor 2 is connected to a ground line through an aluminium interconnection 9. N-type diffused layer 7 constituting a drain of the output transistor 2 is connected to the input/output terminal 1 through an aluminium interconnection 10. The gate electrode 8 is isolated from the aluminum interconnections 9 and 10 by sidewall spacers 16 and an interlayer insulating film 17.
The protective transistor 4 is implemented by a laterally formed NPN bipolar transistor wherein a portion of the P-type semiconductor substrate 5 constitutes a base, N-type diffused layer 7 constitutes a collector and an N-type diffused layer 11 constitutes an emitter. The base region located between N-type diffused layers 7 and 11 is covered by a field oxide film 18. N-type diffused layer 7 constituting the collector of the protective transistor 4 is connected to the input/output terminal 1 through the aluminium interconnection 10. N-type diffused layer 11 constituting the emitter of the protective transistor 4 is connected to the ground line through an aluminum interconnection 12.
In the semiconductor device as described above, the drain of the output transistor 2 and the collector of the protective transistor 4 are formed in common as N-type diffused layer 7, whereby reduction both in the chip area occupied by the semiconductor device and in parasitic capacitance of the input/output terminal 1 can be obtained.